1. Field of the Invention
The present invention relates to a semiconductor memory having testable redundant memory cells and, more particularly, to a semiconductor memory that enables testing of read and write operations with respect to the redundant memory cells of a redundant memory block even before a normal memory cell block with a fault is replaced with a redundant memory block.
2. Description of the Related Art
As a method of relieving defects of a semiconductor memory, a method that entails providing a normal memory cell array and a redundant memory cell array, performing operation tests in a wafer state (primary tests), storing defective cell addresses and so forth in a redundant replacement memory consisting of a PROM with fuses once a defect is detected to replace the defective normal memory cell array with a redundant memory cell array is known. Although a memory chip that has been relieved in this manner becomes a semiconductor memory device after an assembly step in which the memory chip is stored in a package or the like, an operation test (secondary test) is performed in this device state. The cause of a fault in the secondary test is sometimes the occurrence of a fault in the assembly step and sometimes the existence of a fault in the redundant memory cell array that has replaced the normal memory cell array.
Therefore, if a check of whether a fault exists in the redundant memory cell array can be made at the primary test stage, it is possible to eliminate writing to the redundant replacement memory and the following assembly step. Therefore, a method in which an operation test on the redundant memory cell array is permitted at the primary test stage without writing to the redundant replacement memory has been proposed in Japanese Patent Application Laid Open Nos. H05-307896 and H06-243698, for example. These patent documents describe a method in which inputs and outputs to the redundant memory array are enabled by supplying a special signal from the outside without writing relief information to the redundant replacement memory.
In recent years, it has been actively pursued to embed a semiconductor memory in large-scale LSIs such as system LSIs. In this case, the semiconductor memory becomes a memory module. Thus, a primary test must be executed to the semiconductor memory embedded in the LSI and, for reasons similar to those mentioned above, an operation test on the redundant memory array must also be performed in the primary test.
However, according to the methods described in Japanese Patent Application Laid Open Nos. H05-307896 and H06-243698, a special signal must be supplied from the outside in order to enable access to the redundant memory array. Thus, the provision of a special signal in order to access the redundant memory array at the primary test stage necessitates the addition of signal wiring to the memory module, which is undesirable. Further, also in the case of a unit semiconductor memory device, a special terminal for accessing the redundant memory block must be provided, which is disadvantageous.
On the other hand, a semiconductor memory generates a power-on reset signal upon detecting power-on internally and initializes the redundant replacement memory and so forth by means of the power-on reset signal. However, because there are variations in the speed at which the semiconductor memory is powered up at power-on, the internal generation of this power-on reset signal is sometimes not necessarily preferable. In such a case, instead of installing a power-on reset signal generation circuit, a reset signal must be supplied to the memory from the system side and this reset signal must be used to perform in-memory initialization.